Circuit Reliability Through Probabilistic Transfer Matrix

Circuit reliability is a growing concern in today's CMOS electronics, over the years, this has sparked a great deal of interest in reliability-oriented circuit design and reliability analysis. While several approaches to circuit reliability analysis have been published, comparative studies on their benefits and drawbacks in terms of efficiency and accuracy are lacking. This paper offers an overview of the probabilistic transfer matrix approach for reliability analysis, with an emphasis on large and small, gate-level circuits, transistor-level logic gates under stuck-on faults, and transistor failure probability through reliability analysis.