A Power and Delay Efficient Circuit for CMOS Phase Detector and Phase Frequency Detector

Dynamic logic circuits are preferred over CMOS static logic circuits due to the low area and high-speed advantage they offer in high-performance designs. In electronics circuits, the power dissipated by the clock plays a crucial role, and hence research approach in this paper is predominantly centered on the examination of the dynamic logic circuit's comparative performance. This presented work uses the tanner tool to present a novel phase detector (PD) and phase-frequency detector (PFD) using dynamic logic architecture in standard 250nm and 45nm technology. The presented approach optimizes the circuit's speed and power by customizing the conventional approach. The transistor count has been dropped, resulting in lower power consumption and a smaller layout. All the circuit performances like transistor delay, power dissipation, the figure of merit has been optimized. Optimized results are glitch-free and enhance the performance of the circuit. The power supply voltage Vdd is varied in the range of 0.6-1.4 volts and the W/L value for PMOS and NMOS is varied within 1 and 5 to analyze its power and delay performances. These results presented the best possible trade-off between the proposed design in comparison to other existing techniques to optimize area, power, and speed for VLSI circuits.