On-The-Fly Key Generation Based VLSI Implementation of Advanced Encryption Standard

Data transmitted in a digital format is vulnerable to breaches. Here, the FPGA-based Advanced Encryption Standard (AES) architecture is proposed to safeguard high speed data. 128 and 256-bit keys are supported by this implementation. This execution is recursive and processes single block of data containing 128 bits. Giving access towards a series of round keys and a block, the encipher and decipher block handling data paths are isolated. This opens the door to toughen the core wire just to encrypt or decrypt the mechanism. This helps the synthesis/build toolkits to optimize the necessary functionalities which limits the size to around 50 percent. It has been inspected to ensure the complete removal of decryption, and the core is still functioning. This is an implementation that is extremely compact. The design considerations proposed here enable users to build a trade-off between speed, use of resources and consumption of power. The proposed design is evaluated on various FPGA devices and is compared with several existing AES implementations showing area and power optimized through this method.