Design and FPGA implementation of digit-serial fir filters

In this paper the design of a digital-serial N-tap FIR filter with programmable coefficients is presented. The design considers the general case of W-bit sample word and m-bit coefficient word. The processing of the data within the filter takes place with full precision. The output data is truncated to W bits. The design introduced the new digit-serial multiplier that guarantees minimum processing time and reduces the hardware requirements. Sign-amplitude representation for the coefficients and two's complement for the input samples simplified the circuit configuration and allows the use of a single common two's complement circuit for all the filter sections. A 100-tap, 8-bit word length version filter is implemented using an ALTERA FPGA device. The filter can be used in real-time processing with sample rates ranging from 7.5 to 22 MHz