Design of Vedic Mathematics based 16 bit MAC unit for Power and Delay Optimization

Multiply and Accumulate unit is the essential component of any Digital signal processor. In designing such a unit, it is significant to consider various design parameters such as power, area, and delay for a given application. Also, an efficient multiplier and adder units play a vital role in deciding the performance of MAC unit and hence DSP. In this paper, the design of 16 bit MAC unit using 16 bit Vedic multiplier and a 32 bit spanning tree adder is presented. The Vedic multiplier, in turn, is designed utilizing carry save and spanning tree adders by applying the concept of Urdhva Tiryakbhyam sutra. This entire design is coded in Verilog HDL using the tool Xilinx Vivado 2018.3 simulator with a targeting Zedboard (xc7z020-3clg484) for synthesis and implementation. This proposed multiplier design is compared with design of the existing 16 bit Vedic multiplier which is made up of Carry Save Adders. The results showed that there is an improvement in delay and power by 30% and 21.1% respectively compared with the existing design.