Impact of Interface Trap Charge on Analog/RF parameters of Novel Heterogeneous Gate Dielectric Tri-Metal Gate FinFET

In this script, an innovative structure is introduced to optimize TMG FinFET by employing dielectric material engineering. In this method, HfO
2
is placed towards the source side, with SiO
2
towards the drain to enhance the I
ON
and simultaneously suppress I
OFF
for the proposed device. This device is named as heterogeneous gate dielectric tri-metal gate FinFET. Trapping of charges is a common phenomenon that is prominent for nanoscale devices and cannot be neglected. Therefore, a relative study of proposed device with the traditional TMG FinFET is performed along with the investigation of the trapped charges for both FinFETs. It is noticed that the proposed device shows better performance than TMG FinFET. The proposed design shows a negligible influence of interface trap charges, making it suitable for high-frequency, low-power analog/RF applications.