Divider Implementation Based on USP-Awadhoot Division Algorithm For Area Optimization

Algorithm is the systematic way of pursuing any task related to technical or non-technical. The importance of correct algorithms for implementing arithmetic operators is vital in the current electronic era. Amongst all arithmetic operators, divider implementation is a critical affair in electronic computation systems, computer computation systems, embedded computation systems, ASIC computation systems, and high-speed computing systems. As many applications force the use of embedded systems or soft processor-based FPGA systems, it demands area optimization in electronic systems. A sophisticated algorithm is the heart of an embedded, FPGA soft processor, electronic computer system to implement a circuit with a reliable area. Overages, many algorithms are discussed, designed, and implemented, but to evaluate effectiveness in the system, certain aspects like quotient convergence rate, hardware primitives, area overheads, and mathematical formulation, latency time, conversion time need to consider. The Non-restoring SRT algorithm is one of the most implemented digit recurrence algorithms. Though it has a simple conversion logic, it tends to introduce rounding off error if quotient selection logic is not designed properly, and in the case of high radix implementation, this problem gets more critical. Thus, to override rounding off and maintaining the simplicity of conversion logic like the SRT algorithm, we proposed a novel state-of-the-art USP-Awadhood division algorithm implementation in the present article. In this article, we explained the basic stages of the state-of-the-art USP-Awadhood division algorithm and presented the FPGA implementation result indicating area optimization.