Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design

Multipliers are central to modern compute-intensive applications, such as signal processing and artificial intelligence (AI). However, the complex logic chain in conventional multipliers, particularly due to cascaded carry propagation circuits, contributes to high energy and performance costs. This paper proposes a novel current-mode multiplier design that reduces the carry propagation chain and improves the current amplification. Fundamental to this design is a one transistor multi-memristor (1TxM) cell architecture. In each cell, transistor can be switched ON/OFF to determine the cell selection, while the high/low resistive states of memristors determine the corresponding cell output current when selected. The memristor states as well as biasing configurations in each memristor are suitably optimized through a new memristor model. The number of memristors implementing this model in each cell is suitably determined depending on the cell significance to achieve the required amplification. Consequently, the design reduces the need to have current mirror circuits in each current path, while also ensuring high resilience in transitional bias voltages. Parallel cell currents are then directed to a common current accumulation path to generate the multiplier output without requiring any carry propagation chain. We carried out a wide range of experiments to extensively validate our multiplier design in Cadence Virtuoso analogue design environment for functional and parametric properties. The results show that the proposed multiplier reduces up to 85% latency and 99% energy cost when compared with the recently proposed approaches.