Dielectric traps in amorphous silicon oxynitride

As the aggressive scaling of the metal-oxide-semiconductor (MOS) structure continues, new reliability challenges in gate dielectric materials are arising as the gate dielectric thickness is further down-scaled to its technological limits (<4 nm). Since the interface thickness and the capture cross-section of dielectric traps are not scalable, the nanodevice structures and giga-scale circuit architectures call for a fabrication process with ultra-high uniformity and repeatability for each device. These put stronger constraints on the trap density and chemical composition fluctuations of the gate dielectric materials. The paper reviews several important issues for dielectric traps in oxynitride. In particular, the paramagnetic defects (/spl equiv/Si/spl middot/, /spl equiv/Si-O-O/spl middot/, /spl equiv/Si/sub 2/N/spl middot/), diamagnetic defects (/spl equiv/Si-Si/spl equiv/, =N-H), dicoordinated Si center (=Si:) and neutral defects (/spl equiv/SiO/spl middot/, /spl equiv/SiOH, /spl equiv/Si-O-O-Si/spl equiv/) are discussed in detail based on both experimental and simulation results.