Low S/D resistance FDSOI MOSFETs using polysilicon and CMP

In this paper, we report fully depleted silicon-on-insulator (FDSOI) MOSFETs with polysilicon (poly) raised source and drain (S/D) by using chemical mechanical polish (CMP). This poly-raised FDSOI MOSFET, with channel thickness of 30 nm and deposited poly thickness of 80 nm, has shown a 95% reduction in source and drain series resistance and 90% reduction in contact resistance, compared with conventional FDSOI devices with the same channel thickness and without polysilicon at the S/D region. Silicide can be used to further reduce the active resistance.