Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner

Interconnect scaling has been identified as one of the key challenges associated with deeply scaled technology nodes because of several reasons. First, the miniaturization of the metal line and via dimensions not only reduces the cross-sectional area for conduction but also leads to an increase in copper (Cu) resistivity due to sidewall scattering and grain-boundary scattering [1] . Second, the highly resistive barrier/liner (TaN/Ta) layers (required to prevent copper (Cu) diffusion into the surrounding dielectrics) further reduce the cross-sectional area of Cu ( Fig. 1 ), aggravating the first issue. Third, the barrier/liner layers are in the path of the vertical conduction through the vias, which significantly increases the via resistance. To address some of these challenges, replacing the conventional TaN/Ta barriers/liners with ultra-thin 2D transition metal dichalcogenide (2D TMD) material such as TaS
₂
(which serves as both barrier and liner) has been proposed [2] . With only 0.7nm of TaS
₂
(as opposed to 2nm TaN + 2nm Ta), the % volume of Cu in the interconnects can be increased ( Fig. 1 ). However, TaS
₂
suffers from higher vertical resistivity compared to Ta/TaN, which deteriorates the via conductivity. Therefore, evaluation of the overall merits and trade-offs of TaS
₂
-augmented interconnects mandates extensive device modeling and circuit analysis. In this work, we analyze interconnects with TaS
₂
barrier/liner by (a) building a 3D modeling framework for the line metals and vias, (b)integrating the model with the comprehensive circuit simulation flow based on synthesis and place-and-route and (c) evaluating the resistance of different levels of metals (M1-M9) and vias (V1-V8) and the circuit implications of TaS
₂
-augmented interconnects in comparison with the conventional interconnects.