Performance Comparisons of Low-Power Low-Noise CMOS Voltage Controlled Differential Ring Oscillators in 65nm Process

Voltage controlled ring oscillators are essential part of any clock generation/recovery system. Various developments and implementations of these oscillators appear in the literature for different process technologies. In this paper, we have reproduced the results of these novel circuits using publicly available process technology, namely, 65 nm [1]. We have also redesigned the circuits to only have three stages and we have scaled the transistor sizes to suit the process. The results are tabulated side-by-side for comparisons. Design I generated a maximum frequency of 28.5 GHz while design VI occupied the least silicon area of 2.049 (gate area). Design II consumed the least amount of power, 0.02 mW. These results are expected to deviate slightly after post-layout simulation, however, the relative magnitudes should hold true.