Trends in Analog and Digital Intensive Compute-in-SRAM Designs

The unprecedented growth in Deep Neural Networks (DNN) model size has resulted into a massive amount of data movement from off-chip memory to on-chip processing cores in modern Machine Learning (ML) accelerators. Compute-In-Memory (CIM) designs performing DNN computations within memory arrays are being explored to mitigate this `Memory Wall' bottleneck of latency and energy overheads. Among the incumbent embedded memories, the Static Access Random Memory (SRAM) built using high performance logic transistors and interconnects can enable custom CIM designs while offering low pJ/bit access energy, high-endurance, high-performance, and high-bandwidth. The wordline and bitline voltages and pulse-widths are modulated to realize analog or digital domain multiply-and-accumulate (MAC) computations using multiple SRAM bitcell variants. This paper describes the trends in recent CIM-SRAM designs utilizing such analog and digitally-intensive approaches. In an analog CIM-SRAM design, the inputs/activations are transformed into analog voltage or pulsewidth and applied on wordlines and/or bitlines. Multibit MAC computations often involve peripheral data converter circuits which need to be optimized significantly to minimize the area and energy overheads. On the other hand, digitally-intensive CIM-SRAM approaches try to avoid analog circuits by implementing smaller bit-width wordline/bitline computations and utilize sense amplifiers for performing basic logic operations and/or employ small digital logic block next to the SRAM column I/O circuits forming compute-in/near SRAM designs. Key design trends in both the approaches and qualitative comparisons are presented with a perspective on future CIM-SRAM designs.