Biasing Techniques: Validation of 3 to 8 Decoder Modules Using 18nm FinFET Nodes

In this research paper, we planned a low leakage power and high speed decoder for memory cluster application and proposed modern four strategies. In this paper, the collation of source predisposition decoder, source coupling decoder, body bias decoder and cluster decoder are planned and analyzed for memory cluster application. The plan is recreated utilizing Cadence virtuoso with 20nm innovation. The parameters of 3 to 8 decoders designed at 20 nm FinFET nodes using Cadence Virtuoso.