Impact of Ferroelectric Oxide Layer on Palladium Silicide Source Electrode based Double-Gate Junctionless TFET

The Double-Gate (DG) Tunnel Field Effect Transistor (TFET) is widely considered to be the most important emerging device for high-performance computing applications. These devices have proven their ability to achieve the most important requirement of semiconductor industries such as low subthreshold swing (SS<; 60 mV/decade) due to utilization of Band-to-Band Tunneling (BTBT) as a switching mechanism. However, the performance of DG-TFETs is limited to high thermal budget on account of the heavily-doped source and drain region. Although, charge-plasma based Junctionless (JL) device is the alternative solution for a low-thermal budget, but, the combined structure i.e., DG-JL TFET is limited to low I
_ON
along with large subthreshold swing (SS). Therefore, in this work, we have combined the three techniques such as DG, charge-plasma and ferroelectricity in order to achieve better electrostatic control, low thermal budget and low SS (<; 60 mV/decade) respectively. In order to form negative capacitance in DG-JL-TFET structure, a ferroelectric oxide layer i.e., PbZr
_x
Ti
_1-x
O
₃
(0.1<; x<; 1) has been introduced with the control gate silicon dioxide (SiO
₂
) layer. The reported device with the control-gate dielectric stack materials has been found to exhibit low SS of 49.9 mV/decade, switching ratio of 0.75 × 10
⁸
and the threshold voltage of 0.62 V at the supply voltage of 1 V. Silvaco ATLAS tool has been used in the present piece of work for getting out the simulations. The present findings may help to overcome the aforementioned challenges of DG-JL-TFET and thus, the reported device may be used for low-power logic applications.