Novel 9:1 Ternary Multiplexer on 32nm CMOS Technology

Present study explores new 9:1 Ternary-Multiplexer (T-MUX) using Normal Process Enhancement-type Metal Oxide Semiconductor (NPE-MOS) transistors without any threshold modifications. The 3:1 T-MUX based on proposed idea is designed first and that has been exploited in order to design the proposed 9:1 Ternary Multiplexer next. The front end circuit-design and optimization of proposed Ternary Multiplexer is performed on 32nm standard CMOS technology using BSIM4 device model with 1.0V supply rail at 27°C temperature. Ternary-digits "0", "1" and "2" are presented with 0V, 0.5V and 1.0V respectively. The designed circuit has been validated through extensive T-Spice simulations with all possible test patterns. As per evaluation the proposed 9:1 T-MUX consumes 51.37µW average power when operated with 3.2GHz of selection speed. The propagation delay of proposed circuit becomes 15.07ps.