FPGA Implementation of a pipelined and pseudo-randomized TDES algorithm

In today's world where data breaching and misuse of confidential data are so common, an end user's utmost priority should be to keep one's data secure. This is where information security and cryptography comes into the picture and in this paper, a pipelined and pseudo randomized implementation of TDES encryption standard on FPGA using Verilog HDL is designed which can encrypt and decrypt a given user's messages with high throughput and the pseudo randomizer randomizes the key with the help of a Linear Feedback Shift Register which makes the encrypted output random thereby making it more secure than the traditional TDES systems. The target device used is xc7vx330t-3ffg1157 from Virtex-7 FPGA family offered by Xilinx on which a maximum frequency of 608.224 MHz and maximum throughput of 38.92 Gigabits per second was achieved. The proposed design is also faster when compared to previous works on their respective platforms. The proposed system was designed and analyzed thoroughly using the Xilinx ISE Design Suite v14.7.