Optimization of EOR and ENOR for Design of Full Adders with Efficient Transistor Sizing

Full adder circuits are essentially used in bigger circuits like ripple carry adders, carry look ahead adder, multiplier etc. So optimization of full adders plays an important role in digital circuits. A full adder circuit generally consists of EOR, ENOR circuits and the 2x1 Multiplexer. Optimizing the initial stages of the circuit can yield better results for the full adders as a whole. In this paper, as a first step to optimize the full adder, various EOR, ENOR and simultaneous EOR-ENOR circuits have been simulated and analyzed in LTspice XVII using 65nm CMOS technology. All the EOR, ENOR circuits have been compared on the basis of power, average delay and PDP (Power Delay Product) and full swing output. PDP has been used as a figure of merit to compare and discuss about the circuits. Using the obtained EOR, ENOR circuits, four 1-Bit full adder circuits are designed. Each full adder circuit is analysed based on its merits and demerits. The output capacitance of all the simulated circuits is kept at a low range for improved results. A transistor sizing method has been proposed to optimize the PDP of the circuits designed. ABC (Artificial bee colony algorithm) has been implemented using Python3.7 to get the appropriate transistor sizes for all the full adder circuits.