Analogue building blocks for neural-inspired circuits

Hardware implementation of neural networks is an increasingly popular area, both in research and industry. The main motivation is the amazing computational efficiency of the brain together with its self-repairing capability. The subject of artificial neural networks has a long history and much of the advance has been in software environments. Highly complex ‘hidden layers’ of synapses and neurons can be trained in so-called deep learning applications. Implementation in hardware however can bring significant advances in speed. Spiking neural networks (SNN) encode information in the timing of single spikes, and not just in their statistical firing rate [1]. Furthermore, recent neuroscience research has shown that SNNs mimic neuron behaviour on a level more closely related to biology and so have the propensity for powerful computational ability compared to classic artificial neural networks. Simulation platforms have been developed to allow investigation of the role played by spike-timing in the field of computational neuroscience [2]. Hardware approaches based on FPGAs, GPUs and ARM processor cores have been developed for hardware accelerated simulation which could offer such capability at the expense of large silicon area and low energy efficiency [3–5]. Good reviews of the current progress of hardware SNN development can be found in [6–8]. Different neuron models have been adopted varying from very detailed conductance-based approaches to simpler leaky integrate and fire versions. Conductance-based models emulate biophysical ion channels and hence are more faithful to biology. The integrate and fire models are somewhat less biologically realistic but require fewer transistors and can therefore be facilitated with compact layouts with low energy consumption. Thus, designers can balance accuracy with a higher number of neurons in the network, bringing the potential for better scalability. Each of the different implementations offers some trade-off between scalability, latency and biological realism. Finding an appropriate balance between these three elements represents one of the key challenges of hardware SNNs. In this chapter, the integrate and fire approach is explained. A library of dynamically operating analogue functional blocks is described, based on principles, to emulate synaptic behaviour, spike-dependent plasticity, synaptic fan-in, axonal delay and spike bursts. Some schemes for scaling are also described. Finally, ideas for modelling of synaptic self- repair mediated by so-called astrocytes are presented. References to associated publications can be found in the slide set.