90 nm CMOS Resistive Feedback LNA with 34 dB Gain for 25 GHz Applications

The paper presents a 90 nm CMOS Resistive feedback LNA with high gain designed for digital communication receivers operating at 25 GHz. The proposed LNA is based on four-stage configuration. The first and the last stage consist of CS transistors with resistive feedback topology while the second and third stage uses cascode configuration. At 25 GHz, this LNA attains a peak gain of 34.1 dB. With an input of 0.9V, the power consumed by the circuit is 17.3 mW. For achieving a good noise Figure of 2.7 dB at the output port, a $\pi$ matching network is used. The values of S11 (input return loss) and S22 (output return loss) at 25 GHz are -22.3 dB and -23.7 dB respectively.