Comparative Analysis of Low Power Wallace Tree Encoders with Modified Full Adders

Wallace tree encoder is an efficient hardware implementation in VLSI circuits that is used for Analog to digital conversion process. The proposed flash digital to analog converter verified the speed, place and energy. The proposed encoder is designed to counts 1's availed to the logic gates to design the fat tree conversion and ROM encoders. Wallace tree encoder consumes more power so, by constructing low power, high performance Wallace tree encoder using PTL resistor ladder logic with modified full adders, the power can be conserved. The proposed system aims in reducing the number of transistors to get better power efficiency and delay comparator and is efficient in reducing bubble errors. The proposed design will be designed and simulated using Tanner EDA V16 tool.