Three-dimensional (3D) Non-volatile SRAM with IWO Transistor and HZO Ferroelectric Capacitor

We propose a 3D non-volatile SRAM (nvSRAM) design with the experimentally demonstrated BEOL transistors with W doped In
₂
O
₃
(IWO) channel as isolation/access transistors and ferroelectric (FE) Hf
_0.5
Zr
_0.5
O
₂
(HZO) capacitors as non-volatile memory (NVM) elements. The added 4 BEOL transistors and 2 Fe capacitors are integrated on top of a 6 transistor SRAM cell without any area overhead. By decoupling the storage nodes from the FE capacitors, our design can show better retention of the FE capacitors as well as less impact on SRAM read and write static noise margin. The proposed nvSRAM is compatible with advanced technology node (e.g. 28nm or beyond) by delivering the write voltage (V
_w
) for the FE capacitors (~2V) from BEOL transistor while maintain the SRAM at VDD <; =1V. Based on the experimental data from HZO capacitors and IWO transistors, we run SPICE simulation to extract the STORE and RECALL energy. The simulated results suggest that an application with average idle time > 10ms can benefit from the nvSRAM.