Snapback Design Rules for Automotive Vstress Reliability Tests

Voltage Stress (Vstress), a critical integrated circuit (IC) automotive reliability test screen, can be as high as 1.5Vddmax at 150C. This work summarizes a detailed TCAD simulation study of Snapback in 3.3V and 5V Inverters from a high performance grade-0 automotive 0.18um BCD technology. These results demonstrate that Well (Body) tie spacing of NMOS and PMOS is critical in preventing Snapback during high temperature (150C) high voltage (1.5Vddmax) Vstress tests. Therefore, an aggressive Well-tie spacing design rule incorporated during the initial technology development is required to ensure Snapback robustness for such Vstress reliability testing.