A 1.6 GS/s Spectrum Channelizer with PWM-LO Based Sub-band Equalization

A frequency-folded ADC (FF-ADC) [1] partitions the spectrum of an incident signal into N contiguous sub-bands using the harmonics of a switching clock waveform. In this architecture, a broadband input spectrum is downconverted and aliased to baseband by employing N polyphase, non-overlapping rectangular clocks. The aliased sub-bands are bandlimited at baseband, digitized and subsequently channelized employing digital-domain harmonic and image rejection. For a clock period of T_s, with N paths, and a baseband ADC of Nyquist rate of 1/T_s in each path, the effective sampling rate is N/T_s, analogous to a time-interleaved ADC (TI-ADC) [2]. In applications with a significant variation in the sub-band signal power, sub-bands with large power can reduce the available ADC dynamic range for other sub-bands with lower power. A similar issue is observed at the input of a broadband TI-ADC as well. Architectures for gain-scaling of sub-bands in an FF-ADC to relax this issue are described in [3], [4]. In [5], a receiver with non-overlapping LOs that can select an arbitrary number of harmonics but reject other harmonics by applying sinusoidal gain coefficients at baseband, is described.