Power Efficient Dynamic Comparator for High Speed Digital Circuit

ADCs (Analog-Digital converters) are the main designing elements & implemented in various applications for digitization of the signals. The dynamic comparator is one of the crucial modules of ADC design. A new type of dynamic comparator is proposed in the paper, in which changes are made to circuitry of traditional double tail comparator for purpose of faster execution & less consumption of power. The control transistor is introduced in proposed design to achieve higher speed. The power is also reduced by including switching transistors. The results are simulated using 45 nm technology using Tanner tool. The proposed comparator is almost 6 times faster than conventional double tail comparator and 15 time faster than conventional dynamic comparators. In proposed comparator the power consumption is reduced 85% with respect to conventional double tail comparator and 35% in comparison of the conventional comparator.