Novel Bit-Sliced Near-Memory Computing Based VLSI Architecture for Fast Sobel Edge Detection in IoT Edge Devices

For today’s Internet-of-Things (IoT) edge devices, there is an acute need for fast and power-efficient hardware for an image processing task. Traditional hardware solutions with sequential and/or pipelined architectures incur high latency and power. This motivates us to propose a novel near-memory computing architecture for rapid image processing. We propose a bit-sliced near-memory computing architecture for CMOS VLSI implementation for fast Sobel edge detection in IoT edge devices. To the best of our knowledge, this is the first work to propose near-memory computing based VLSI architecture for edge detection. The novelty of the proposed work is that one image can be processed in constant time irrespective of the image size. Binary images are used as input to the design. The Sobel operator equations are simplified by operator strength reduction, bit manipulation, and common term sharing across equations. The captured image is loaded into the design and all block-level operations are executed in parallel close to where the data resides. The architecture is highly modular and can be scaled for any image size. The block processing element (PE) is implemented at the gate-level with the Synopsys Design Compiler in 32 nm CMOS technology node using SAED 32/28 nm Process Design Kit. For processing one block frame (3x3 pixel block), the number of logic gates required is 22 with a worst-case delay of 1.5 fs and a total area of 111 n m
²
. The average power dissipation is 2.27 μW at 1.05 V supply voltage.