An FPGA-based 3D-2D RANSAC Architecture for Matching Feature Points in RGB-D Slam

In RGB-D slam, 3D-2D RANSAC is an algorithm widely used to eliminate the mismatch between 3D camera coordinates. In this paper, an FPGA-based 3D-2D RANSAC architecture is proposed to achieve hardware acceleration. By simplifying matrix operations and reusing results, the calculation in the process of calculating hypothetical parameters is reduced by 67%. Besides, the architecture is pipelined to enhance the ability of image processing. In addition, self-regulation of the number of iterations is supported, which effectively speeds up the convergence of the iterative process. The proposed architecture is capable of processing any number of matching pairs between 42048, while reaching 130MHz on the Xilinx XC7V2000T FPGA platform. In the case of 2048 matching pairs which takes the most time per iteration, the system handles 126 fps video stream, and thus real-time requirement is met.