Hardware Implementation For Fast Block Generator Of Litecoin Blockchain System

The development of blockchain-based cryptocurren-cies has attracted a lot of interest in many fields, especially in academic research. Besides Bitcoin, Litecoin is one of the most popular cryptocurrency based on blockchain currently. The Litecoin mining process uses the Scrypt algorithm as a hash function in Proof-of-Work (PoW) consensus mechanism. The yield of cryptocurrency mining depends a lot on the processing performance of the hardware. Therefore, this paper proposes a hardware design of the Scrypt algorithm in the Litecoin mining system using the Verilog hardware description language (HDL). In the proposed design, the pipeline technique is applied at two levels: the overall Scrypt level and the PBKDF2 level. Additionally, the design is divided into several stages to reduce the latency of each clock cycle and increase the operating frequency. The simulation and verification of the design are performed based on Atlys Spartan-6 FPGA Board and Xilinx Virtex-7 FPGA VC707. The performance of the design evaluated on Atlys Spartan-6 has the hash rate of 2209 hashes/s. The maximum operating frequency of the system is 147.059MHz. On Xilinx Virtex-7, the hash rate of the design reaches 5332 hashes/s and the maximum operating frequency reaches 355.051 MHz.