Implementation of Error Correction Techniques in Memory Applications

As the technology scales down, various soft errors in SRAM memories occurs due to which the single cell and multiple cell upsets are formed. Error correction codes such as the first technique (7,4) hamming code, where 7 denotes total code word, four refers to data bits and 3 parity bits were implemented and verified its encoding and decoding process. But it is only useful for single bit error detection and also correction, which has been the main drawback of this hamming code. So, the second technique implemented was the extended hamming code (8,4) or SEC-DED code ("Single Error Correction-Double Error Detection"). This code has an extra bit and used for correction of single error and also detection of double error. But correction of double error doesn’t happen in SEC-DED code. So, the extension of (8,4) SEC-DED code was (14,8) SEC-DED-DAEC ("Single Error Correction-Double Error Detection-Double Adjacent Error Correction") code where 14 denotes total code word, 8 data bits, six parity bits which can be used for correction of single error, detection of double error and also correction of double adjacent error was proposed in this work. These techniques related Encoding and Decoding processes were studied and all the simulation results were verified and implemented by using Verilog Coding in Xilinx ISE 14.7 tool. This proposed SEC-DED-DAEC method was also implemented in memory application and its output is verified. The double error detection was adjacently corrected by using this method and the complexity was decreased. The advantage of the proposed technique is it has the ability to detect and correct errors adjacently up to 2 bits.