Design and Implementation of CORDIC algorithm using Integrated Adder and Subtractor

CORDIC (Coordinate Rotation Digital Computer) has been designed and implemented in many variants in the past five decades where the different architectures of the algorithm were used in many diverse applications. CORDIC algorithm is a flexible shift and add algorithm having an important feature of reduced quantization errors in the case of higher word lengths when compared to other algorithms. The major issue with the algorithm is due to its linear rate convergence with the speed of iteration. Its overall performance is also affected due to repeated number of shift and adds operations and thereby leading to high power consumption. The main aim of this work is to use a new integrated adder and subtractor designed using reversible gates in the place of binary adders and subtractors used in the previous design. This improved CORDIC uses an architecture where the rotation angle is split into micro rotation angles, where these angle sets provides faster convergence by reducing the number of iterations. Overall performance of the proposed algorithm is implemented using variety of FPGA families like Virtex-4, Virtex-5 and Artix-7 devices with comparison to parameters like area, frequency and power consumed. It is compared with the Conventional CORDIC and LH CORDIC designs.