A DHT-based FFT/IFFT processor for VDSL transceivers

This paper presents a new VLSI architecture for computing the N-point discrete Fourier transform (DFT) of real data and the corresponding inverse (IDFT) based on the discrete Hartley transform, where N is a power of two. The architecture includes two real multipliers, three real adders, six memory-based buffers, two ROMs, and some simple logic circuits, making itself suitable for single-chip implementation. It is capable of evaluating one DFT sample or one IDFT sample every (log/sub 2/N+1)//sub 2/ clock cycles on average. Under 0.35 /spl mu/m CMOS technology, the proposed design can operate at a clock rate of 100 MHz to reach a throughput of 20M transform samples per second for N=512. The processing speed will be higher if more advanced CMOS technology is adopted to implement the same circuit. Such low-complexity and high-throughput feature supports that the proposed design is well suited for use in discrete multitone based very high-speed digital subscriber line transceivers.