A digital chip for robust speech recognition in noisy environment

A digital chip has been developed for isolated word recognition in real-world noisy environments. By carefully comparing recognition performance and hardware implementability a modified-ZCPA model and RBF neural network model are selected for the feature extractor and classifier, respectively. The modified-ZCPA model is based on the feature extraction mechanism of the human auditory system, and demonstrated superiority for noisy speech. The RBF network has excellent OOV (out-of-vocabulary) rejection capability as well as good recognition performance. Both the feature extractor and classifier are implemented by repetition of simple operations, which result in reduction of memory operations for the full use of memory bandwidth. The chip is custom designed at logic level without any DSP core, and implemented with an FPGA with 12 MHz clock speed.