Designing Optimized Topologies for On-Chip Massive Data Communication

Now more processing elements are laid on a single chip to process massive data concurrently, and the on-chip networks thus are becoming more and more important. As contention for communication resources has strong impact on the execution of a parallel program, and it is difficult to get the communication pattern of an application in advance, the parallel program needs to have good performance under any stochastic task mapping strategy. This manuscript presents a new method for designing new on-chip network topologies and gives theoretical analysis to the designed topologies. The analysis results show that compared with some classical topologies, although the designed topologies have lower vertex degrees, they can achieve good properties in terms of network diameter, average latency, and throughput. If we take advantage of higher levels of VLSI process and increase the vertex degree, we can design topologies with even better communication properties. Simulation results show that the designed topologies can significantly improve the performance of parallel applications.