Abstract:
Errors of vector-matrix-multiplication induced by interconnect resistance become a crucial reliability challenge in non-volatile memory (NVM) based neural network. Here, ...Show MoreMetadata
Abstract:
Errors of vector-matrix-multiplication induced by interconnect resistance become a crucial reliability challenge in non-volatile memory (NVM) based neural network. Here, we propose a novel weight mapping method, called weight mapping correction (WMC), to mitigate the deviation of weight represented by the conductance of NVM array without time-consuming retraining and circuit overheads. Simulation results show that accuracy is recovered significantly when WMC is applied to various size arrays consisting of mainstream NVM in advanced technology nodes.
Date of Conference: 21-25 March 2021
Date Added to IEEE Xplore: 26 April 2021
ISBN Information: