Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node

Logic soft-error rates are expected to exceed latch soft-error rates at advanced technology nodes due to operating frequencies in the GHz range. Predictive models for logic soft-errors need difficult-to-obtain data for single-event transient pulse widths. This work proposes an empirical method for estimating logic soft-error rates using shift registers designed with conventional D flip-flops at the 7-nm node. Availability of this model will provide insight to designers on logic soft-error contributions during the design stages.