TCMP and CHIPPER Router design for Power Efficient Network on Chips

Network on Chip (NoC) is an emerging design platform for on chip connections which overcomes issues faced by conventional bus build communication. The main aim in design of any NoC is to reduce average latency and deflection rate without reducing the operating speed. To overcome the surge in design area as well as Static and Dynamic power consumption issues in case on normal VC (Virtual Channel) based router, deflection routing concept has been suggested. The routing process used in case of BLESS (Buffer Less Router) depends upon deflection of packets to an unintended port. To curtail excess power consumption and design area, researchers have come up with buffer less and littlest buffer router. In this paper Tiled Chip Multiple Processor (TCMP) and CHIPPER router parameter details are discussed. Permutation deflection logic is used in this paper. Results shows that as compared to normal VC Buffer router, CHIPPER Router reduces Normalized Router area by 36.2% compared to BLESS Router, Normalized Critical Path is reduced by 29.1% while is almost same as compared to a normal VC Buffer Router