A Study on Various Approaches in Designing Ternary Half Adder

The arithmetic addition operation, performed by adder, is the prime function of all arithmetic computation in logic systems. In logical systems, adders are present in arithmetic logic units (ALU), multipliers, dividers etc. In this paper, various design implementations for ternary half adder (THA) are analyzed and discussed. Some of the design approaches are based on ternary logic gates (decoder-encoder), combination of ternary and binary logic, multiplexer based, transmission gates, etc. Some THA are approached with different technology like CMOS, CNTFET and GNRFET. The main purpose is to reduce area, power and delay. The design of THA started with TSUM operator, followed by various methods like resistive-load CNTFET, combination of ternary and binary logic, replacement of AND-OR logic by NAND-NOR logic. The aim of presenting this paper is to bring together different approaches in designing ternary half adder (THA)using different technologies, devices and materials. And also to assist new design developers and to showcase the developed design methodologies.