Low-Complexity Parallel Cyclic Redundancy Check

Cyclic redundancy check (CRC) is adopted in many digital communication and storage systems to ensure data integrity. CRC en/decoding is carried out using linear feedback shift registers (LFSRs) and a parallel LFSR can be implemented by registers with a feedback matrix multiplication and an input pre-processing matrix multiplication. A large parallelism is needed to achieve the high throughput required by modern applications. In prior designs, the complexity of parallel LF- SRs has been reduced by applying state transformation and/or modifying the input tap. In this paper, we first show that the input tap modification can be actually described by a category of state transformation. Using this type of transformation, the pre-processing matrix in a highly-parallel LFSR can be simplified without changing the feedback matrix. Additionally, we show that the post-processing matrix multiplication in state-transformed designs can be eliminated without affecting the error detection capability of the CRC. Utilizing these two techniques, the area requirement of highly-parallel CRC can be reduced by 7-16% without increasing the critical path for various parallelisms and most generator polynomials compared to the best previous design.