A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop

Double-edge triggered flip-flops (DETFF) project a solution to clock power reduction by lowering the clock frequency and maintains the same data rate. Hence, they are appropriate to be used as shift registers. This paper has reviewed several earlier designs of double-edge triggered flip-flops and presented an 8-bit low power shift register by using a newly designed DETFF. The major contribution of this work takes advantage of two parallel data paths that work in opposite phases of the single clock without an inverted input trigger. The proposed shift register design is realized using a typical 90-nm CMOS process. The post-layout results show that the proposed shift register reduces the power consumption by at least 17.2%.