An Approximate and Iterative Posit Multiplier Architecture for FPGAs

Recently, many applications have demanded cheaper and faster arithmetic while providing a wider dynamic range than the popular IEEE 754 floating-point (FP) arithmetic. As a result, a new number format called posit was proposed. As in a variety of number systems, multiplication in posit arithmetic is one of the most frequently used but expensive operations. To reduce the number of hardware resources in a posit multiplier, this paper applies an iterative approach to posit multiplication. To exploit the features of the posit format, the number of truncated bits in the fraction component is dynamically changed depending on the number of regime bits. In addition, architectures for fast parser and packer are proposed. Thanks to the posit format, the proposed design supports about 60 decades wider dynamic range than a single-precision FP multiplier design. Using the iterative approach, the proposed design also reduces the number of lookup tables used in a previous exact posit multiplier design by 44% while achieving a 51% higher maximum frequency, and the appropriate balance between latency and accuracy can be finely determined at runtime. To the best of the authors' knowledge, this paper is the first work that proposes a hardware architecture of an approximate and iterative posit multiplier.