A Fully Synthesizable All-Digital Phase-Locked Loop with Parametrized and Portable Architecture

The article presents an all-digital phase-locked loop (ADPLL) design method based on standard cells. A new portable architecture introduced. Its motor is a fully synthesizable description of a digital controlled oscillator (DCO) with variable length ring oscillator (VLRO) as coarse part and fine-tune unit based on path selector of different pin-to-pin delays in NAND standard cell. Time to digital converter (TDC) circuit with a two- level structure has been added to reduce the oscillator frequency's initial coarse-tune time. TDC allows finding the desired output frequency in two reference clock cycles. The two- level structure reduces the hardware costs of implementing this block. The circuit is designed using standard library cells only and is described in Verilog HDL. This enables design automation and simplifies the design of digital signal processing circuits for modern System-on-a-Chip.