10-bit SAR ADC Design in a Double-Poly 180 nm CMOS Process

This paper presents the design of a 10-bit successive-approximation analog-to-digital converter (SAR ADC). The general circuit of ADC has a correction circuit for a sample-and-hold device. The correction circuit allows to fit transfer characteristic of the ADC and reduce its deviation from ideal to ± 1 of the least significant bit. For the target 180 nm CMOS process the ADC power dissipation is less than 8 mA, and the occupied area is 0.1485 mm².