Identification of Integrated Circuits Based on Layout Layers Routing Information

Protection of intellectual property (IP) in field of EDA is a highly important task. Integrated Circuit (IC) copy detection could be only performed using the final IC layout data. Due to the fact that the final IC layout contains huge amount of geometries to analyze, it is clear that this task is very difficult. Existing techniques to verify the IP of the ICs are mostly based on two approaches: watermarks injection and layout geometries mutual placement identification. In our work we propose an algorithm for calculating some kind of "layout hash" which is based on information about IC layout layers routing.