Analysis of High Speed Hybrid Full Adder

Multiplier plays an important role in the design of FIR filters in digital signal processors (DSP). In VLSI the multipliers performance speed affects the overall speed of the system. Moreover, multiplication process uses execution time in most of the DSP devices. Hence, high speed is required in multiplier. This paper presents the analysis of a high speed new radix-4 multiplier using Shannon adder. The proposed hybrid adder is implemented in order to achieve higher reduction of power in the high speed parallel radix-4 multiplier. Hence this modified radix-4 multiplier is a suitable candidate for obtaining less propagation delay, low power consumption and better power delay product. The circuit simulations are done using Synopsys H-Spice software. The obtained simulation results exhibit that the proposed structure performance is better in terms of Propagation delay, low power consumption and Power delay product when compared with the advanced technology in CMOS.