A High PSRR, Low Ripple, Temperature-Compensated, 10-μA-Class Digital LDO Based on Current-Source Power-FETs for a Sub-mW SoC

State-of-the-art digital low-dropout regulators (LDOs) have shown competitive dynamic load regulation at a scaled output capacitor size. However, achieving high power-supply-rejection-ratio (PSRR) and small output ripple in a digital LDO remains a challenge. We present a digital LDO targeted for a sub-mW system-on-a-chip, featuring current-source-based power-FETs and hybrid event-/time-driven digital control. The prototype in 65-nm achieves -32-dB PSRR with 126-nA quiescent current, 10.9-mV worst-case output ripple, 58.1 ppm/°C temperature stability, and 0.15-pF dynamic load regulation figure-of-merit (pF-FoM).