10-Bit Successive Approximation Register Analog-to-Digital Converter for BLDC Motor Drive

This paper presents a 2.27 MS/s 10-bit successive approximation register (SAR) analogue-to-digital converter for BLDC motor drive by using a TSMC 0.25 μm 1P3M CMOS process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). In TSMC 0.25μm 1P3M CMOS process, the N-type buried layer (NBL) is applied to boost the withstanding voltage at the expense of shorting all PMOS bodies and failing in design a buffer circuit. Those faults limits the circuit design to avoid from connecting the source with body for PMOS. Then the single-end input topology is a superior choice. Post-layout-simulated results show that the signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 65.88 dB, 10.65 bits, 833 μW, and 1.35 × 0.98 mm², respectively.