Design of a Built-in-Self-Test Implemented AES Crypto Processor ASIC

This paper presents the design of a (built-in self-test) BIST implemented Advanced Encryption Standard (AES) crypto-processor Application-Specific Integrated Circuit (ASIC). Hardware implementation provides higher speed and better physical security than that of software implementation. One of the burning issues is the testability of a complex VLSI chip. This research addresses this problem by implementing a mixed-mode BIST technique into the chip. The ASIC is designed using Verilog Hardware Description (HDL). It works both in normal mode and test mode. In test mode, the test manager enables an LFSR and initializes it with seed value from the memory and generates the desired number of pseudorandom and deterministic test patterns which are applied to the AES ASIC and outputs are compressed into a signature through the output response analyzer (ORA) which is compared with that of the pre-stored golden signature kept in the memory. If both the signatures match each other then the ASIC is ensured as fault-free otherwise it is faulty. The ASIC is simulated in two platforms: Java and ModelSim to ensure its proper functionality which has been verified using NIST provided input and output.