Design and Analysis of 10T SRAM Cell with Stability Characterizations

Nowadays, the use of Static random-access memory (SRAM) is increasing in System on Chip and VLSI circuits with the arrival of portable devices. Our main focus of research is SRAM optimization because most parts of the chip are used by memories. In today's world, the main requirement of the industry is low power and high-performance memories. The scaling of CMOS devices gives rises to a various problem which can be overcome by FinFET device. In this paper a novel 10T SRAM cell design using FinFET is present at different technologies. A detailed comparison is carried out with a 10T CMOS cell for 45nm and 32nm technologies. For analysis purpose different parameters of SRAM such as power, static noise margin (SNM) and delay are taken into considerations. Improvement in the hold and read static noise margins (HSNM, RSNM) by 31% and 29% at 45nm and 41% and 50% at 32nm of FinFET based SRAM cell is obtained compared to CMOS based cell. Simulations have been carried out on the HSPICE tool at a supply of 0.5v and temperature of 25°C temperature.