A Fault-tolerant Method of SRAM FPGA Based on Processor Scrubbing

In order to improve the reliability of FPGA in space applications, a method of single event upset detection and scrubbing based on internal processor is proposed for Xilinx Zynq device. We propose a method to reduce the sensitive configuration bits and consequently the global scrubbing time based on Xilinx Essential Bits technology. Then the impact on reducing sensitive frames by placing different layout constraints is analyzed. The physical address of one single configuration frame and its corresponding configuration data are obtained based on the configuration memory structure. Simultaneously, Frame_ECC primitive and global CRC circuit is added to the design. Finally, the feasibility of our system is verified by the fault injection, and the time performance is evaluated by Mean Time to Detect (MTTD). The results show that the system can effectively shorten the readback and scrubbing time, single-bit upset and multi-bit upsets can be detected and repaired. Thus, the work is of great significance for improving the reliability of aerospace electronic systems.