Design of Two Stage Operational Amplifier and Implementation of Flash ADC

In this paper, Flash Analog to digital converter is implemented whose resolution is 3-bits. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using LTspice tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Binary code is obtained from the thermometer code by utilizing a priority encoder. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the power consumption of the ADC by optimizing encoder circuitry. With the purpose of reducing power consumption, Encoder is implemented using 2:1 mux based on various logics such as switch logic, pass transistor logic as well as CMOS logic. In addition to this, the Wallace tree encoder was also implemented. Performance parameters of Flash ADC such as conversion time as well as average power are calculated and compared. It is verified average power obtained using Wallace tree encoder is 910pW and it is less compared to encoder implemented with other designs.